Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices comprise integrated circuits (IC) that are formed on semiconductor wafers by depositing many types of thin films of materials over the semiconductor wafers. The thin films are patterned to form electronic components, such as transistors, diodes, resistors, capacitors, etc. The transistors may be metal-oxide-semiconductor field-effect transistors (MOSFET), or fin field-effect transistors (FinFET). ICs are increasingly more complex with millions of components such as transistors connected together to perform intended functions.
An IC may be created by a design process starting with a software description, e.g., in a programming language such as C or VHDL, of the functionality of the circuit. The software description is then synthesized to interconnected gate-level hardware elements. Next the hardware elements and their connections are physically laid out, represented as placements of geometric shapes, often referred to as a layout, on a variety of layers to be fabricated on semiconductor wafers. In general, the geometric descriptions are polygons of various dimensions, representing conductive or non-conductive features located in different layers over the semiconductor wafers. After the IC design process is completed, an IC layout is created. The layout is then design-rule checked and verified to be equivalent with the desired design schematic. This step is generally referred to as design-rule check (DRC) and layout versus schematic (LVS).
As minimal features of electronic components are decreasing, interactions are increasing among transistors in closer proximity, as well as between transistors and interconnect layers. Parasitic circuit elements are increasingly affecting the performance of an IC. The resistance and capacitance (RC) extraction step, also called as parasitic extraction, is performed following the DRC and LVS step, in order to extract electrical characteristics of the layout. The RC extraction step converts a physical design layout back into representative electrical circuit elements, and measures the actual shapes and spaces in the layers of a layout to predict the resulting electrical characteristics of the manufactured chip. The electrical characteristics that are commonly extracted from a physical design layout include capacitance and resistance in the electronic devices and on the various interconnects, which are generally referred to as “nets”, that electrically connect the aforementioned devices.
Various Electronic Design Automation (“EDA”) or Computer Aided Design (CAD) tools may be used in the design process to handle the complexity of the design, and to perform the DRC, LVS, and RC extraction. Current CAD tools for RC extraction have issues with accuracy, and speed, and may not be able to handle FinFET process well. New methods and apparatus are needed to achieve high accuracy, fast speed, and for FinFET process.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.